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rt8073 ? ds8073-01 november 2012 www.richtek.com 1 copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. ? ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. general description the rt8073 is a high efficiency pwm step-down converter and capable of delivering 6a output current over a wide input voltage range from 2.9v to 5.5v. the rt8073 provides accurate regulation for a variety of loads with an 1% reference voltage at room temperature. for reducing inductor size, it provides up to 2mhz switching frequency. the efficiency is maximized through the integrated 50m for high side, 35m for low side mosfets and 250 a typical supply current. the rt8073 features over current protection, frequency fold back function in shorted circuit, hiccup mode under voltage protection and over temperature protection. the rt8073 is available in sop-8 (exposed pad) and wdfn-12l 3x3 packages. 6a, 2mhz, high efficiency synchronous step- down converter features z z z z z integrated 50m and 35m mosfets z z z z z 6a output current z z z z z high efficiency up to 95% z z z z z 2.9v to 5.5v input range z z z z z adjustable pwm frequency : 300khz to 2mhz z z z z z 0.8v 1% reference voltage z z z z z adjustable external soft-start z z z z z power good indicator (wdfn-12l 3x3 only) z z z z z over current protection z z z z z under voltage protection z z z z z over temperature protection z z z z z sop-8 (exposed pad) and 12-lead wdfn packages z rohs compliant and halogen free applications z low voltage, high density power systems z distributed power systems z point-of-load conversions rt8073 package type sp : sop-8 (exposed pad-option 2) qw : wdfn-12l 3x3 (w-type) lead plating system g : green (halogen free and pb free) simplified application circuit vin rt8073 lx boot comp v out rt en l c boot c out r fb1 r fb2 c in v in fb gnd r t r c c c marking information rt8073gsp rt8073gsp : product number ymdnn : date code rt8073gqw 5c= : product code ymdnn : date code rt8073 gspymdnn 5c=ym dnn
rt8073 2 ds8073-01 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. functional pin description pin configurations (top view) sop-8 (exposed pad) wdfn-12l 3x3 comp gnd en vin fb rt boot lx pgnd 2 3 4 5 6 7 8 9 comp pgood vin en fb rt lx lx lx ss vin boot 11 10 9 1 2 3 4 5 12 67 8 pgnd 13 pin no. sop-8 (exposed pad) wdfn-12l 3x3 pin name pin function 1 1 comp compensation node. 2 -- gnd analog ground. 3 4 en chip enable. externally pulled high to enable and pulled low to disable this chip, and it is internally pulled up to high when the pin is floating. 4 5, 6 vin power input. 5 7 boot bootstrap supply for high side gate driver. 6 8, 9, 10 lx switch node. 7 11 rt frequency setting. 8 12 fb feedback voltage input. 9 13 (exposed pad) pgnd power ground. the exposed pad must be shouldered to a large pcb and connected to pgnd for maximum power dissipation. -- 2 pgood power good indicator with open drain output. it is high impedance when the output voltage is regulated. it is internally pulled low when the chip is shutdown, thermal shutdown or vin is under uvlo threshold. -- 3 ss soft-start control.
rt8073 3 ds8073-01 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. function block diagram for sop-8 (exposed pad) package for wdfn-12l 3x3 package en vin lx fb oscillator current sense shutdown control uvlo driver control logic pgnd pwm comparator error amplifier voltage reference soft-start boot slope compensation rt en threshold comp gnd over temperature protection v in internal pull up current en vin lx fb oscillator current sense shutdown control uvlo driver control logic pgnd pwm comparator error amplifier voltage reference soft- start boot slope compensation ss rt over temperature protection en threshold pgood comp v in internal pull up current v in power good threshold
rt8073 4 ds8073-01 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. operation the rt8073 is a current mode synchronous step-down dc/dc converter with two integrated power mosfets. it can deliver up to 6a output current from a 2.9v to 5.5v input supply. the rt8073's current mode architecture allows the transient response to be optimized over a wide input voltage and load range. cycle-by-cycle current limit provides protection against shorted outputs and soft-start eliminates input current surge during start-up. error amplifier the error amplifier adjusts comp voltage by comparing the feedback signal (v fb ) from the output voltage with the internal 0.8v reference. when the load current increases, it causes a drop in the feedback voltage relative to the reference, the comp voltage then rises to allow higher inductor current to match the load current. oscillator (osc) the frequency of the oscillator is adjustable by an external resistor connected between the rt pin and gnd. the available switching frequency range is from 300khz to 2mhz. pgood comparator when the feedback voltage (v fb ) rises above 94% or falls below 106% of reference voltage, the pgood open drain output will be high impedance. the pgood open drain output will be internally pulled low when the feedback voltage (v fb ) falls below 90% or rises above 110% of reference voltage. soft-start (ss) an internal current source charges an external capacitor to build the soft-start ramp voltage (v ss ). the v fb voltage will track the v ss during soft-start interval. the chip will use internal soft-start if the ss pin is floating. the nominal internal soft-start time is 800 s. over temperature protection (otp) the rt8073 implements an internal over temperature protection. when junction temperature is higher than 165 c, it will stop switching operation. once the junction temperature decreases below 145 c, the rt8073 will automatically resume switching.
rt8073 5 ds8073-01 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. recommended operating conditions (note 4) z supply input voltage, vin ----------------------------------------------------------------------------------------- 2.9v to 5.5v z junction temperature range -------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range -------------------------------------------------------------------------------------- ? 40 c to 85 c absolute maximum ratings (note 1) z supply input v oltage, vin ----------------------------------------------------------------------------------------- ? 0.3v to 6.5v z boot to lx ----------------------------------------------------------------------------------------------------------- ? 0.3v to 6v z other pins ------------------------------------------------------------------------------------------------------------- ? 0.3v to (v in + 0.3v) z power dissipation, p d @ t a = 25 c sop-8 (exposed pad) --------------------------------------------------------------------------------------------- 2.041w wdf n-12l 3x3 ------------------------------------------------------------------------------------------------------- 1.667w z package thermal resistance (note 2) sop-8 (exposed pad), ja ---------------------------------------------------------------------------------------- 49 c/w sop-8 (exposed pad), jc --------------------------------------------------------------------------------------- 15 c/w wdfn-12l 3x3, ja ------------------------------------------------------------------------------------------------- 60 c/w wdfn-12l 3x3, jc ------------------------------------------------------------------------------------------------- 7.5 c/w z lead temperature (soldering, 10 sec.) ----------------------------------- -------------------------------------- 260 c z junction temperature ----------------------------------------------------------------------------------------------- 150 c z storage temperature range -------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body model) ---------------------------------------------------------------------------------------- 2kv parameter symbol test conditions min typ max unit input power supply under voltage lockout threshold v uvlo v in rising -- 2.6 2.8 v quiescent current i q active, v fb = 0.9v, not switching -- 250 -- a shutdown current i shdn -- 2 5 a voltage reference voltage reference v ref 0.792 0.8 0.808 v enable logic-high v ih 1.5 -- 5.5 en input voltage logic-low v il -- -- 0.4 v switching frequency setting 300 -- 2000 r t = 28.7k -- 1400 -- switching frequency f osc rt pin is floating -- 300 -- khz minimum on-time -- 80 -- ns minimum off-time -- 60 -- ns (v in = 5v, c in = 10 f, t a = 25 c, unless otherwise specified) electrical characteristics
rt8073 6 ds8073-01 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. note 1. stresses beyond those listed ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions may affect device reliability. note 2. ja is measured at t a = 25 c on a high effective thermal conductivity four-layer test board per jedec 51-7. jc is measured at the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. parameter symbol test conditions min typ max unit mosfet high side mosfet on-resistance v in = 5v, boot ? lx = 5v -- 50 -- m low side mosfet on-resistance v in = 5v -- 35 -- m current limit current limit threshold 7 9 -- a power good v fb rising (good) -- 94 -- v fb falling (fault) -- 90 -- v fb rising (fault) -- 110 -- power good range (wdfn-12l 3x3 only) v fb falling (good) -- 106 -- % v ref over temperature protection thermal shutdown rising -- 165 -- c thermal shutdown hysteresis -- 20 -- c
rt8073 7 ds8073-01 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. typical application circuit v out (v) r fb (k ) r fb2 (k ) r c (k ) c c (nf) l ( h) c out 3.3 75 24 33 0.33 0.47 cer. 20 f + e-cap 100 f 2.5 51 24 24 0.47 0.47 cer. 20 f + e-cap 100 f 1.8 30 24 18 0.56 0.47 cer. 20 f + e-cap 100 f 1.5 21 24 15 0.68 0.33 cer. 20 f + e-cap 100 f 1.2 12 24 12 1 0.33 cer. 20 f + e-cap 100 f 1 6 24 10 1 0.33 cer. 20 f + e-cap 100 f table 1. recommended component selection rt8073 lx boot comp v out rt ss l c boot 0.1f r fb1 r fb2 r t 28.7k c ss 10nf r c c c chf* fb pgnd gnd c out1 10f c out3 47f to 100f c out2 10f * : option vin pgood r pg 100k c in2 c in1 10f v in 10f en chip enable
rt8073 8 ds8073-01 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. output voltage vs. output current 1.02 1.04 1.06 1.08 1.10 1.12 1.14 1.16 1.18 0.0 0.6 1.2 1.8 2.4 3.0 3.6 4.2 4.8 5.4 6.0 output current (a) output voltage (v) v out = 1.1v v in = 5v v in = 4v v in = 3.3v efficiency vs. load current 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 load current (a) efficiency (%) v out = 1.1v v in = 3.3v v in = 4v v in = 5v output voltage vs. input voltage 1.00 1.02 1.04 1.06 1.08 1.10 1.12 1.14 1.16 1.18 1.20 2.5 3 3.5 4 4.5 5 5.5 input voltage (v) output voltage (v) v out = 1.1v output voltage vs. temperature 1.06 1.07 1.08 1.09 1.10 1.11 1.12 1.13 1.14 1.15 1.16 -50 -25 0 25 50 75 100 125 temperature (c) output voltage (v) v in = 5v, v out = 1.1v, i out = 1.5a typical operating characteristics frequency vs. input voltage 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 2.5 3 3.5 4 4.5 5 5.5 input voltage (v) frequency (mhz) 1 v out = 1.1v, i out = 1.3a switching frequency vs. temperature 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 -50 -25 0 25 50 75 100 125 temperature (c) switching frequency (mhz) 1 v out = 1.1v, i out = 1.3a
rt8073 9 ds8073-01 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. v in = 5v, v out = 3.3v, i out = 6a time (250ns/div) output ripple voltage v out (20mv/div) v lx (5v/div) v in = 5v, v out = 1.1v, i out = 0a to 3a time (100 s/div) load transient response v out (100mv/div) i out (2a/div) v in = 5v, v out = 1.1v, i out = 0a to 6a time (100 s/div) load transient response v out (100mv/div) i out (2a/div) v in = 5v, v out = 1.1v, i out = 6a time (250ns/div) output ripple voltage v out (20mv/div) v lx (5v/div) currrent limit vs. temperature 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 -50 -25 0 25 50 75 100 125 temperature (c) currrent limit (a) v in = 5v, v out = 1.1v currrent limit vs. input voltage 7.0 7.5 8.0 8.5 9.0 9.5 10.0 2.5 3 3.5 4 4.5 5 5.5 input voltage (v) currrent limit (a) v out = 1.1v
rt8073 10 ds8073-01 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. time (10ms/div) power off from en v out (2v/div) v en (5v/div) i lx (5a/div) v in = 12v, v out = 1.05v, i out = 3a time (250 s/div) power on from en v out (2v/div) v en (5v/div) i lx (5a/div) v in = 5v, v out = 3.3v, i out = 6a time (10ms/div) power off from vin v out (2v/div) v in (5v/div) i lx (5a/div) v in = 5v, v out = 3.3v, i out = 6a time (1ms/div) power on from vin v out (2v/div) v in (5v/div) i lx (5a/div) v in = 5v, v out = 3.3v, i out = 6a
rt8073 11 ds8073-01 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. application information the basic rt8073 application circuit is shown in typical application circuit. external component selection is determined by the maximum load current and begins with the selection of the inductor value and operating frequency followed by c in and c out . output voltage setting the output voltage is set by an external resistive divider according to the following equation : fb1 out ref fb2 r vv1 r ?? =+ ?? ?? rt8073 gnd fb r fb1 v out r fb2 figure 1. setting the output voltage soft-start (ss) an internal current source charges an external capacitor to build the soft-start ramp voltage (v ss ). the v fb voltage will track the v ss during soft-start interval. the chip will use internal soft-start if the ss pin is floating. the nominal internal soft-start time is 800 s. with external soft-start, the typical soft-start time can be calculated as following equation : t ss (ms) = 0.1 x c ss (nf) for example, if c ss = 10nf, the soft-start time is 1ms. operating frequency selection of the operating frequency is a tradeoff between efficiency and component size. high frequency operation allows the use of smaller inductor and capacitor values. operation at lower frequency improves efficiency by reducing internal gate charge and switching losses but requires larger inductance and/or capacitance to maintain low output ripple voltage. the operating frequency of the rt8073 is determined by an external resistor that is connected between the shdn/ rt pin and gnd. the value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator. the rt resistor value can be determined by examining the frequency vs. rt curve. although frequency as high as 2mhz is possible, the minimum on-time of the rt8073 imposes a minimum limit on the operating duty cycle. the minimum on-time is typically 80ns. therefore, the minimum duty cycle is equal to 100 x 80ns x f (hz). figure 2 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 20 40 60 80 100 120 140 160 180 200 rt (k ) switching frequency (mhz) 1 chip enable operation the en pin is the chip enable input. pulling the en pin low (<0.4v) will shut down the device. during shutdown mode, the rt8073 quiescent current drops to lower than 2 a. driving the en pin high (>1.5v, 5.5v) will turn on the device again. for external timing control, the en pin can also be externally pulled high by adding a r en resistor and c en capacitor from the vin pin (see figure 3). where v ref equals to 0.8v (typical) the resistive divider allows the fb pin to sense a fraction of the output voltage as shown in figure 1. figure 3. enable timing control rt8073 en gnd v in r en c en en
rt8073 12 ds8073-01 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. an external mosfet can be added to implement digital control on the en pin when no system voltage above 1.5v is available, as shown in figure 4. in this case, the pull-up resistor, r en , is connected between v in and the en pin. mosfet q1 will be under logic control to pull down the en pin. figure 4. digital enable control circuit rt8073 en gnd v in r en q1 en slope compensation and inductor peak current slope compensation provides stability in constant frequency architectures by preventing sub-harmonic oscillations at duty cycles greater than 50%. it is accomplished internally by adding a compensating ramp to the inductor current signal. normally, the maximum inductor peak current is reduced when slope compensation is added. in the rt8073, however, separated inductor current signals are used to monitor over current condition. this keeps the maximum output current relatively constant regardless of duty cycle. hiccup mode for the rt8073, it provides hiccup mode under voltage protection (uvp). when the output is shorted to ground, the uvp function will be triggered to shut down switching operation. if the under voltage condition remains for a period, the rt8073 will retry automatically. when the under voltage condition is removed, the converter will resume operation. the uvp is disabled during soft-start period. figure 5. hiccup mode under voltage protection inductor selection the inductor value and operating frequency determine the ripple current according to a specific input and output voltage. the ripple current i l increases with higher v in and decreases with higher inductance. out out l in vv i = 1 fl v ??? ? ?? ??? ? ??? ? out out l(max) in(max) vv l = 1 fi v ??? ? ? ??? ? ??? ? having a lower ripple current can reduce not only the esr losses in the output capacitors but also the output voltage ripple. however, it requires a large inductor to achieve this goal. for the ripple current selection, the value of i l = 0.4(i max ) will be a reasonable starting point. the largest ripple current occurs at the highest v in . to guarantee that the ripple current stays below the specified maximum, the inductor value should be chosen according to the following equation : the inductor's current rating (caused a 40 c temperature rising from 25 c ambient) should be greater than the maximum load current and its saturation current should be greater than the short circuit peak current limit. time (1ms/div) hiccup mode v out (500mv/div) i lx (5a/div) v out short to gnd
rt8073 13 ds8073-01 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. layout considerations follow the pcb layout guidelines for optimal performance of rt8073. ` a ground plane is recommended. if a ground plane layer is not used, the signal and power grounds should be segregated with all small-signal components returning to the gnd pin at one point that is then connected to the pgnd pin close to the ic. the exposed pad should be connected to gnd. ` connect the terminal of the input capacitor(s), c in , as close as possible to the vin pin. this capacitor provides the ac current into the internal power mosfets. ` lx node is with high frequency voltage swing and should be kept within small area. keep all sensitive small-signal nodes away from the lx node to prevent stray capacitive noise pick-up. ` flood all unused areas on all layers with copper. flooding with copper will reduce the temperature rise of power components. ` connect the fb pin directly to the feedback resistors. the resistor divider must be connected between v out and gnd. figure 6. derating curve of maximum power dissipation thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of the ic package, pcb layout, rate of surrounding airflow, and difference between junction and ambient temperature. the maximum power dissipation can be calculated by the following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature, and ja is the junction to ambient thermal resistance. for recommended operating condition specifications, the maximum junction temperature is 125 c. the junction to ambient thermal resistance, ja , is layout dependent. for sop-8 (exposed pad) packages, the thermal resistance, ja , is 49 c/w on a standard jedec 51-7 four-layer thermal test board. for wdfn-12l 3x3 packages, the thermal resistance, ja , is 60 c/w on a standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formulas : p d(max) = (125 c ? 25 c) / (49 c/w) = 2.041w for sop-8 (exposed pad) package p d(max) = (125 c ? 25 c) / (60 c/w) = 1.667w for wdfn-12l 3x3 package the maximum power dissipation depends on the operating ambient temperature for fixed t j(max) and thermal resistance, ja . the derating curves in figure 6 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 0 25 50 75 100 125 ambient temperature (c) maximum power dissipation (w ) wdfn-12l 3x3 four-layer pcb sop-8 (exposed pad)
rt8073 14 ds8073-01 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. figure 7. pcb layout guide for wdfn-12l 3x3 figure 8. pcb layout guide for sop-8 (exposed pad) comp pgood vin en fb rt lx lx lx ss vin boot 11 10 9 1 2 3 4 5 12 67 8 pgnd 13 v out gnd r fb1 r fb2 r t l c boot c out gnd c in gnd r en c ss r good c c r c gnd lx should be connected to inductor by wide and short trace, keep sensitive components away from this trace. output capacitor must be near rt8073 connect the fb pin directly to feedback resistors. the resistor divider must be connected between v out and gnd. c in must be placed between vin and gnd as closer as possible. comp gnd en vin fb rt boot lx pgnd 2 3 4 5 6 7 8 9 v out r fb1 r fb2 gnd r t l c boot c out c in r en c c r c gnd gnd output capacitor must be near rt8073 lx should be connected to inductor by wide and short trace, keep sensitive components away from this trace. c in must be placed between vin and gnd as closer as possible. connect the fb pin directly to feedback resistors. the resistor divider must be connected between v out and gnd. table 2. inductors component supplier series inductance ( h) dcr (m ) current rating (a) case size wurth elektronik no.744308033 0.33 0.37 27 1070 wurth elektronik no.744355147 0.47 0.67 30 1365 table 3. capacitors for c in and c out component supplier part no. capacitance ( f) case size tdk c3225x5r0j226m 22 1210 tdk c2012x5r0j106m 10 0805 panasonic ecj4yb0j226m 22 1210 panasonic ecj4yb1a106m 10 1210 taiyo yuden LMK325BJ226ML 22 1210 taiyo yuden jmk316bj226ml 22 1206 taiyo yuden jmk212bj106ml 10 0805 recommended component selection for typical application
rt8073 15 ds8073-01 november 2012 www.richtek.com ? copyright 2012 richtek technology corporation. all rights reserved. is a registered trademark of ric htek technology corporation. outline dimension a b j f h m c d i y x exposed thermal pad (bottom of package) 8-lead sop (exposed pad) plastic package dimensions in millimeters dimensions in inches symbol min max min max a 4.801 5.004 0.189 0.197 b 3.810 4.000 0.150 0.157 c 1.346 1.753 0.053 0.069 d 0.330 0.510 0.013 0.020 f 1.194 1.346 0.047 0.053 h 0.170 0.254 0.007 0.010 i 0.000 0.152 0.000 0.006 j 5.791 6.200 0.228 0.244 m 0.406 1.270 0.016 0.050 x 2.000 2.300 0.079 0.091 option 1 y 2.000 2.300 0.079 0.091 x 2.100 2.500 0.083 0.098 option 2 y 3.000 3.500 0.118 0.138
rt8073 16 ds8073-01 november 2012 www.richtek.com richtek technology corporation 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 richtek products are sold by description only. richtek reserves the right to change the circuitry and/or specifications without notice at any time. customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a richtek product. information furnish ed by richtek is believed to be accurate and reliable. however, no responsibility is assumed by richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of r ichtek or its subsidiaries. dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 d 2.950 3.050 0.116 0.120 d2 2.300 2.650 0.091 0.104 e 2.950 3.050 0.116 0.120 e2 1.400 1.750 0.055 0.069 e 0.450 0.018 l 0.350 0.450 0.014 0.018 w-type 12l dfn 3x3 package 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options

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